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Circuits & Systems Classroom

PCI Express

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Guided tour · 1 of 8

One road for each device

PCI Express connects the CPU to the chips and cards around it: graphics cards, SSDs, network cards. The old PCI bus made every card share one set of wires; PCIe gives each device a link of its own, point to point. Data travels on it in packets, the coloured trains here, slowed down about 25 million times.

Look forPackets leave the CPU on the left and reach the device on the right, while short messages come back the other way.

Link

Generation
Lanes

Gen 3 (2010) · 8 GT/s per lane · 128b/130b · 4.00 GB/s raw each way

Packets

256 B
Header

90.0% of the line rate is data · serialization per packet 71.1 ns

Round trip

100 ns
40 ns
8

A slot returns no sooner than 311 ns. 5 slots cover this round trip.

Playback

40 ns/s

Each second shows 40 ns of the link: 25 million times slower than real

Key

  • start of packet + sequence number
  • header · header of a resent copy
  • payload: the data
  • LCRC: the error check
  • damaged by noise
  • ACK · NAK · credit, coming back
After line coding3.94GB/s
Data arriving now0.00GB/s

Raw rate: 4.00 GB/s each way. Payload ceiling: 3.60 GB/s (90.0% of raw). Buffer slots and device service limit utilization to 100%.

0 sent · 0 resent · 0 NAKs
Each generation, x4GB/s each way

Linear scale, after line coding or CRC/FEC. Gen 2 → 3 rises from 5 to 8 GT/s; coding efficiency also improves. Click to switch.

Share of the link that is datapayload size
0%25%50%75%100%1632641282565121k2k4k
Data rate against packet slotslimit measured
0%25%50%75%100%18162432

One slot per packet is a teaching abstraction. PCIe has separate posted, non-posted and completion header/data credit pools. ACKs can be cumulative; this model replies to every TLP and omits return-link serialization.

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