Integer-`N` vs fractional-`N`

One reference, one loop, one VCO. Only the divider differs.

Referencef_ref

MHz

Loop bandwidthBW 1 MHz

Model notes

Simulation. Reference-rate time-domain model of both loops: 40 960 reference cycles, the first 8 192 discarded. Spectrum of e^jφ with a Hann window.

Jitter. RMS of the output edge-time error against an ideal clock at f_out, one sample per reference cycle, so it integrates from f_ref/32 768 to f_ref/2. Integer-N jitter comes only from the assumed noise below; the extra jitter of fractional-N is produced by the divider.

Assumed noise. Reference and phase detector: white, normalised floor −228 dBc/Hz, so in-band noise is −228 + 10 log f_ref + 20 log N (634 fs rms per edge). VCO: −120 dBc/Hz at 1 MHz. The same noise realisation drives both PLLs.

Loop. Linear phase detector, type-II filter with ζ = 1 and two extra poles at six times the bandwidth. The closed-loop −3 dB bandwidth is set directly, from 100 kHz up to f_ref/12 (at most 5 MHz); the loop stays stable with about 1.5 dB of peaking over that range.

Divider. Accumulator and MASH 1-1-1 are 24-bit; the ΣΔ word has its LSB set. DTC: ideal gain, a range of four VCO periods, parabolic INL.

Target output

GHz

integer-N: multiples of 40 MHz fractional-N: any frequency

Integer-N

f_out = N · f_ref

N = 125 5.0000 GHz misses target by 5 MHz

Fractional-N

f_out = (N + α) · f_ref

N + α = 125.1250 5.0050 GHz on target

Integer-NPhase detectorfeedback edge vs reference edge, per cycle

Fractional-NPhase detectorfeedback edge vs reference edge, per cycle

Integer-NOutput spectrumoffset from carrier RMS jitter 188 fs (1.2 kHz–20 MHz) · largest spur none

Fractional-NOutput spectrumoffset from carrier RMS jitter 4.33 ps (1.2 kHz–20 MHz) · largest spur −20.5 dBc at 5 MHz