Circuits & Systems Classroom

Pipeline ADC

+0.100%
0.000%
0.680000 V
12-BIT OUTPUT101011100001code 2785
Errors active: S1Each stage keeps its own settings
Actual Ideal · 12-bit, nonredundant
0 missing codes

Each row expands the selected interval above

Original input · V
Progressive magnification through all 4 pipeline stagesEvery row plots the original ADC input in volts. Each row expands the selected input interval in the row above; numerical axis limits show the magnification. Amplifier rows have a fixed residue axis from -0.1 to 1.1 volts; the final row shows the flash digit on its code scale. Colored solid curves are actual, gray dashed curves ideal. Dots follow the same sample.Stage 1: residue versus original Vin, 0–1 V · gain error 0.1% · nonlinearity 0%Stage 13b · residue V1.1-0.10.500.51×8 zoomStage 2: residue versus original Vin, 0.625–0.75 VStage 23b · residue V1.1-0.10.50.6250.6880.75×8.008 zoomStage 3: residue versus original Vin, 0.6718281718281718–0.6874375624375625 VStage 33b · residue V1.1-0.10.50.67180.67960.6874×8 zoomStage 4: final flash digit versus original Vin, 0.6796328671328671–0.681584040959041 VStage 43b · Flash digit700.679630.680610.68158Every x axis: original Vin · V

DNL

-0.001 … 0.510 LSB
DNLOutput code: 0 to 4096. DNL · nominal LSB: -0.6 to 0.6. -0.001 … 0.510 LSB. Selected point: 2785.5, -0.000999000998945121.-0.600.601024204830724096DNL · nominal LSBOutput code

INL · endpoint fit

-0.446 … 0.447 LSB
INL · endpoint fitTransition code: 0 to 4096. INL · fitted LSB: -0.5 to 0.5. -0.446 … 0.447 LSB. Selected point: 2785, 0.1227025486237479.-0.500.501024204830724096INL · fitted LSBTransition code

ADC transfer

ADC transferOriginal input · V: 0 to 1. Output · V: -0.1 to 1.1. Gray dashed: ideal. Colored solid: actual. Selected point: 0.68, 0.6800537109375.-0.10.51.100.250.50.751Output · VOriginal input · V

Every stage, one conversion

Each stage resolves b bits: q = clamp(floor(2ᵇu), 0, 2ᵇ − 1), DAC = q / 2ᵇ, and ideal residue r = 2ᵇ(u − DAC). The final flash adds bits without another residue amplifier. The 10-stage preset is 9 × 1 bit + 3 bits = 12 bits.

Each residue amplifier independently produces F(r) = (1 + g)r + 4nr(1 − r)(2r − 1), where g and n are the two percentage settings divided by 100. The cubic term preserves both endpoints. Outside the nominal residue range 0–1 V, the amplifier follows the endpoint tangent to preserve a monotonic overrange response. Analog residue is never clipped; subsequent digital decisions saturate. Errors in every configured stage act together, and each architecture retains its own settings. Reset errors clears all stages; Random errors changes only the stage being edited; Random all changes the input and every stage.

DNL[k] = (T[k + 1] − T[k]) / LSB − 1, with nominal LSB = 1 / 4096 V. It includes the measured widths of the first and last bins. A zero-width code has DNL = −1. INL uses a line through the first and last observed transitions, in fitted LSBs; unreachable transitions are omitted. Current fit: transitions 1–4095.

Every stage is visible together. Each row enlarges the original-input interval selected by the preceding digital decisions. The horizontal axis is original Vin in every row, with explicitly different bounds. The highlighted interval expands into the next row; its displayed zoom ratio is a viewing scale, not the residue amplifier gain. The ideal voltage range is 0–1 V; residue and ADC transfer voltage axes stay fixed at -0.1 to 1.1 V. Gray dashed curves show the ideal response; colored solid curves show the actual response on the same axes. The last row shows the final flash digit on its integer code scale. DNL and INL retain the full code range. Numerical extrema and the INL endpoint fit always use the full input range.

This is a static, nonredundant pipeline model. Redundant decision stages, digital correction, settling and noise are not modeled.

Save the current view to reproduce a problem or continue with the same settings.